Semiconductor integrated circuits wafers are produced by a plurality of processes in a wafer fabrication facility (fab). These processes, and associated fabrication tools, may include deposition, polishing, grinding, thermal oxidation, diffusion, ion implantation, rapid thermal processing (RTP), chemical vapor deposition (CVD), physical vapor deposition (PVD), epitaxy, etch, and photolithography. During the fabrication stages, products (e.g., semiconductor wafers) are monitored and controlled for quality and yield using metrology tools. As integrated circuits feature sizes are reduced, the amount of monitoring and controlling may need to be increased. This, however, increases costs by the increased quantity of metrology tools required, the increased manpower to perform the monitoring and controlling, and the associated delay in manufacturing cycle time. Furthermore, identification of failure at later metrology stage may not initiate earlier action and introduce even higher manufacturing cost.
Electric performances, such as interconnect resistance or through silicon via (TSV) connectivity yield, can only be measured at wafer acceptance test (WAT) or chip probe (CP) stages. These measurement stages are usually very far behind key process stages. This will greatly limit possible remedy actions, such as rework, pre-screening for scrap or process control. This problem is even tougher when detecting TSV yield. In current practice, yield measurement is only possible on products with daisy chain structures, while this is not practical on customer products. For customer TSV products, especially interposer, there is no effective yield measurement method. Measurement time delay makes rework not feasible. Measurement time delay makes advanced process control (APC) not feasible. Additionally, pre-screening for reducing cost is not feasible.
Therefore, what is needed is system and method for an integrated circuit fabrication integrated with monitoring, predicting and controlling a quality and/or yield of IC products.